Voltage regulators are well known in the art. These devices attempt to provide a stable, nearly constant (regulated) supply voltage to a load. Further, these devices attempt to maintain the supply voltage at the nearly constant value regardless of the current demands of the load. In one practical application, voltage regulators are utilized in complex electronic systems to convert an unregulated supply voltage (e.g., from a battery) into a regulated supply voltage of a predetermined value that is supplied to one or more discrete components of the complex electronic systems.
Complex electronic systems incorporating components such as microprocessors, field programmable gate arrays (FPGAs), and digital application specific integrated circuits (ASICs) often require voltage regulators that can perform ramp control functions of their regulated output voltages at startup and shutdown. Such complex systems typically “ramp up” their internal system power at startup in response to the assertion of an externally supplied enable control signal (i.e., a control signal passed to the system from an external source through a device pin), and “ramp down” their internal system voltages at shutdown (i.e., when the enable control signal is de-asserted).
This invention relates to voltage regulators for complex electronic systems that provide “ramped up” (often referred to as “soft-start”) startup voltages and “ramped down” (often referred to as “soft-stop”) shutdown voltages. The soft-start and soft-stop functions control system components at startup and shutdown such that supply voltages rises at a known controlled rate at startup, stop reliably at the programmed operating voltage without overshoot, and then decrease at a controlled rate at shutdown. The soft-start function is particularly used to control inrush currents in capacitors, minimize load surges in battery sources, or to moderate the effect of voltage spikes. The soft-start function typically utilizes a user-supplied external capacitor that is mounted to a dedicated external pin of the voltage regulator. A small current applied to this soft-start capacitor during the startup process causes the charge stored in the capacitor to gradually increase, and this gradually increasing charge is utilized to produce the ramped voltage signal. During soft-stop operations, the current applied to the soft-start capacitor is reversed, and the voltage ramps down as the soft start capacitor discharges.
It is often desirable that devices of a complex system have delayed response to the de-assertion of the enable control signal, allowing time for “ramp down” of power, or simply a grace period of good power after the enable control signal is de-asserted. To accomplish this, some conventional voltage regulators may use ‘derivative enable’ wherein the leading edge of enable is used to signify ‘turn on’, and the trailing edge to signify ‘turn off’. This approach is subject to multiple failure modes due to transient conditions at the load or at VIN. Such transients may cause a shut down of the basic bandgap biasing, leaving the device ‘dead in the water’ due to a short transient phenomenon. This effectively amplifies a short-term transient into a system wide failure.
What is needed is a method and structure for controlling the operation of a voltage regulator that both provides soft-start/soft-stop functionality and resists shut down of the basic bandgap biasing in response to a short transient event, thereby preventing undesirable system wide failures due to such short transient events.